Patents:

"Microprocessor and Method for Detecting Faults Therein ", USPTO number 7,966,538 B2

Conference Publications:

1	"MLP Aware Heterogeneous Memory System ", Design, Automation and Test in Europe (DATE), 2011
2	"Ultra Low-Cost Defect Protection for Microprocessor Pipelines", Proc. of the XII International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2006.
3	"VOLTaiRE: Low-cost Fault Detection Solutions for VLIW Microprocessors", Proc. of Workshop on Introspective Architecture (WISA), 2006.
4	"On Design and Implementation of an Embedded Automatic Speech Recognition System", IEEE International Conference on VLSI Design, 2004.

Technical Reports:

1	"Variable Delay Gate Design and Clock Grid Simulation", Concise Internship Report, AMD Boston, Fall 2006 (for confidentiality purposes, I cannot publish the full report with results. I have an outline of the work here).
1	"Towards An Efficient Low Frequency Energy Recovery Dynamic Logic", Prelims Report, EECS Dept., Univ. of Michigan, Ann Arbor, 2005.
2	"A Pipelined Architecture for a Reconfigurable FSM based Router", M.Tech Dissertation, IIT Bombay, 2004.

Projects:

1	"Design of a VLIW Alpha processor with Online Testing", chip designed in TSMC 0.18μm CMOS technology with a cycle accurate simulator in C for verification, 2005.
2	"Design of a JPEG decoder", chip designed in 0.25μm CMOS technology with a custom datapath, Huffman decoder, Run length decoder and Booth Multiplier, 2004.
3	"Design of a Automatic Speech Recognition system"; involved coding of the algorithm, design of a custom DSP board around the TI 2407 DSP and an accomapnying FM wireless link for remote applicance control.

Chip Layouts and Project photos: