I am a PhD candidate at the EECS Dept., University of Michigan, Ann Arbor. I work in the real time computing lab with Prof. Kang Shin.

My research interests include low power hardware design, computer microarchitecture and system reliability.

I am currently working on low power architecture techniques for minimizing power dissipation in multi core processors and the memory system.

My interests include fault tolerant architectures and online fault detection and speech recognition. (CV found under research and pubs)

I was working as an intern with AMD, Boston during fall 2006, where I was part of the high performance clocking team.

I have also worked with Prof. Marios Papaefthymiou on energy recovery circuit design techniques to design a low power adder. More details of my work is to be found under research on the left.

Last updated on 19^th Jan, 2009.

©  Sujay Phadke