Nilmini Abeyratne

About Me

Ph.D. Candidate
Computer Engineering Laboratory
Computer Science and Engineering
University of Michigan

Advisor Professor Trevor Mudge

4856 Beyster Bldg.
2260 Hayward Street
Ann Arbor, MI 48109-2121

Nilmini Abeyratne

I am a Ph.D. student in the Computer Science and Engineering Department at the University of Michigan. I do research in computer architecture related to high performance computing.

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Google Scholar

Checkpointing for exascale supercomputers:

Efficient checkpointing is imperative for resilience to failures in future supercomputers. My paper, Checkpointing Exascale Memory Systems with Existing Memory Techonolgies, proposes fast and reliable checkpointing that only requires commercial off-the-shelf (COTS) memory devices in order to create a low-risk checkpointing framework, without relying on speculative, emerging non-volatile memories.

Network topologies for kilo-core chips:

As processor designs move toward having an increasing number of cores, the on-chip network must scale to support increase demand for bandwidth. My paper, Scaling Towards Kilo-Core Processors with Asymmetric High-Radix Topologies, looks at the scalability of some well-known topologies. In addition, the paper proposes two hierarchical topologies that can scale to hundreds of cores.

Quality-of-service for on-chip networks:

The ability to provide QoS is important for systems running real time applications. In the interconnect, which is a shared resource, QoS is about regulating network bandwidth such that each application receives its required bandwidth without degrading the performance of other concurrently running applications. Currently, I am trying to design an interconnect that has built-in QoS support.

Checkpointing Exascale Memory Systems with Existing Memory Technologies
Nilmini Abeyratne, Hsing-Min Chen, Byoungchan Oh, Ronald Dreslinski, Chaitali Chakrabarti, and Trevor Mudge. The Second International Symposium on Memory Systems (MEMSYS 2016).
[Paper: pdf]

Enhancing DRAM Self-Refresh for Idle Power Reduction
Byoungchan Oh, Nilmini Abeyratne, Jeongseob Ahn, Ronald Dreslinski, and Trevor Mudge. 2016 International Symposium on Low Power Electronics and Design (ISLPED 2016).
[Paper: pdf] [Poster: pdf] [bib]

Quality-of-Service for a High-Radix Switch
Nilmini Abeyratne, Supreet Jeloka, Yiping Kang, David Blaauw, Ronald Dreslinski, Reetuparna Das, and Trevor Mudge. 51st Design Automation Conference (DAC 2014).
[Paper: pdf] [Slides: pdf] [bib]

Scaling Towards Kilo-Core Processors with Asymmetric High-Radix Topologies
Nilmini Abeyratne, Reetuparna Das, Qingkun Li, Korey Sewell, Bharan Giridhar, Ronald G. Dreslinski, David Blaauw, and Trevor Mudge. 19th IEEE International Symposium on High Performance Computer Architecture (HPCA 2013).
[Paper: pdf] [Slides: pptx] [bib]