| About Me | Ph.D. Candidate |
| Advisor | Professor Trevor Mudge |
| sabeyrat@umich.edu | |
| Address | 4856 Beyster Bldg. |
I am a Ph.D. student in the Computer Science and Engineering Department at the University of Michigan. I do research in computer architecture related to high performance computing.
Checkpointing for exascale supercomputers:Efficient checkpointing is imperative for resilience to failures in future supercomputers. My paper, Checkpointing Exascale Memory Systems with Existing Memory Techonolgies, proposes fast and reliable checkpointing that only requires commercial off-the-shelf (COTS) memory devices in order to create a low-risk checkpointing framework, without relying on speculative, emerging non-volatile memories. |
Network topologies for kilo-core chips:As processor designs move toward having an increasing number of cores, the on-chip network must scale to support increase demand for bandwidth. My paper, Scaling Towards Kilo-Core Processors with Asymmetric High-Radix Topologies, looks at the scalability of some well-known topologies. In addition, the paper proposes two hierarchical topologies that can scale to hundreds of cores. |
Quality-of-service for on-chip networks:The ability to provide QoS is important for systems running real time applications. In the interconnect, which is a shared resource, QoS is about regulating network bandwidth such that each application receives its required bandwidth without degrading the performance of other concurrently running applications. Currently, I am trying to design an interconnect that has built-in QoS support. |
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Checkpointing Exascale Memory Systems with Existing Memory Technologies |
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Enhancing DRAM Self-Refresh for Idle Power Reduction |
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Quality-of-Service for a High-Radix Switch |
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Scaling Towards Kilo-Core Processors with Asymmetric High-Radix Topologies |