Memory dependence prediction establishes a read after write dependence between a store and a load instruction. If the processor accurately predicts the data dependence be-tween a store and a subsequent load, we can completely bypass memory and forward the data directly from the store'sproducer to the load's consumer. Our simulation studies show that even in the case of processors with oracle depen-dence predictors, memory bypassing only provides a 2.3% IPC improvement over dependence prediction alone. Giventhe small potential gains in the ideal case and the hardware complexity required to implement memory bypassing, we argue that computer microarchitects should focus on memory dependence prediction and ignore memory bypassing.