Publications


  • Experiences Using the RISC-V Ecosystem to Design an Accelerator-Centric SoC in TSMC 16nm
    Ajayi, Tutu and Al-Hawaj, Khalid and Amarnath, Aporva and Dai, Steve and Davidson, Scott and Gao, Paul and Liu, Gai and Lotfi, Atieh and Puscar, Julian and Rao, Anuj and Rovinski, Austin and Salem, Loai and Sun, Ningxiao and Torng, Christopher and Vega, Luis and Veluri, Bandhav and Wang, Xiaoyang and Xie, Shaolin and Zhao, Chun and Zhao, Ritchie and Batten, Christopher and Dreslinski, Ronald G. and Galton, Ian and Gupta, Rajesh K. and Mercier, Patrick P. and Srivastava, Mani and Taylor, Michael B. and Zhang, Zhiru. In First Workshop on Computer Architecture Research with RISC-V (CARRV), oct 2017.
    [PDF] [BibTeX]

  • Celerity: An Open Source RISC-V Tiered Accelerator Fabric
    Ajayi, Tutu and Al-Hawaj, Khalid and Amarnath, Aporva and Dai, Steve and Davidson, Scott and Gao, Paul and Liu, Gai and Lotfi, Atieh and Puscar, Julian and Rao, Anuj and Rovinski, Austin and Salem, Loai and Sun, Ningxiao and Torng, Christopher and Vega, Luis and Veluri, Bandhav and Wang, Xiaoyang and Xie, Shaolin and Zhao, Chun and Zhao, Ritchie and Batten, Christopher and Dreslinski, Ronald G. and Galton, Ian and Gupta, Rajesh K. and Mercier, Patrick P. and Srivastava, Mani and Taylor, Michael B. and Zhang, Zhiru. In Symposium on High Performance Chips (Hot Chips), aug 2017.
    [PDF] [BibTeX]

  • A Carbon Nanotube Transistor based RISC-V Processor using Pass Transistor Logic
    Amarnath, Aporva and Feng, Siying and Pal, Subhankar and Ajayi, Tutu and Rovinski, Austin and Dreslinski, Ronald G.. In Proceedings of the 2017 International Symposium on Low Power Electronics and Design (ISLPED), jul 2017.
    [PDF] [BibTeX]

  • Neurosurgeon: Collaborative Intelligence Between the Cloud and Mobile Edge
    Kang, Yiping and Hauswald, Johann and Gao, Cao and Rovinski, Austin and Mudge, Trevor and Mars, Jason and Tang, Lingjia. In Proceedings of the 22nd International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), apr 2017.
    [PDF] [BibTeX]

  • Sirius Implications for Future Warehouse Scale Computers
    Hauswald, Johann and Laurenzano, Michael A. and Zhang, Yunqi and Li, Cheng and Rovinski, Austin and Khurana, Arjun and Dreslinski, Ronald G. and Mudge, Trevor and Petrucci, Vinicius and Tang Lingjia and Mars, Jason. In IEEE Micro Top Picks, 36(3), May–June 2016.
    [PDF] [BibTeX]

  • Designing Future Warehouse-Scale Computers for Sirius, an End-to-End Voice and Vision Personal Assistant
    Hauswald, Johann and Laurenzano, Michael A. and Zhang, Yunqi and Yang, Hailong and Kang, Yiping and Li, Cheng and Rovinski, Austin and Khurana, Arjun and Dreslinski, Ronald G. and Mudge, Trevor and Petrucci, Vinicius and Tang, Lingjia and Mars, Jason. In ACM Transactions on Computer Systems (TOCS), 34(1), April 2016.
    [PDF] [BibTeX]

  • Sirius: An Open End-to-End Voice and Vision Personal Assistant and Its Implications for Future Warehouse Scale Computers
    Hauswald, Johann and Laurenzano, Michael A. and Zhang, Yunqi and Li, Cheng and Rovinski, Austin and Khurana, Arjun and Dreslinski, Ronald G. and Mudge, Trevor and Petrucci, Vinicius and Tang, Lingjia and Mars, Jason. In Proceedings of the 20th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), mar 2015.
    [PDF] [BibTeX]


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