SOI

SOI stands for "Silicon On Insulator". In comparison with standard silicon technology, this technique offers the possiblility of fabricating electronic circuitry on a wafer which electrically isolates the circuitry from substrate. The substrate associated problems in standard technology , such as parasitic capacitance, considerable leakage current and isolation with other nearby devices, can be eliminated with SOI. The first confirmation that SOI is becoming the state-of-art technology came when IBM launched the first fully-functional SOI mainstream microprocessor in 1999. The IBM predicted the processor fabricated on an SOI SIMOX(separated by implanted oxide) would lead to 25-35% improvement.

It is suggested that MEMS accelerometer, Analog read-out circuit and core microprocessor be integrated on a same wafer without any hybrid connections to outside components. Generally processing MEMS structure and circuit together requires special connection techniques because of high step difference between MEMS structure and circuit, in addition to compatible fabrication process for both. However, in our suggested configuration, the expected connection problems between MEMS structures and circuits can be resolved by maintaining the same surface levels between them, which enables the deposition step coverage better.

Additional References:

1. F. Udrea, et. all. "SOI Power Devices", in Electronics & Communication Engineering Journal, February 2000, pp. 27-40.
2. Srinath Krishnan and Jerry G. Fossum "Grasping SOI Floating Body effects, in Circuits and Devices", July 1998, pp. 32-37.

    

Advantages of SOI

Conventional bulk CMOS circuitry is facing formidable issues, such as the needs to reduce threshold voltage (Vt) and increase operating frequency. As a solution of those problems, some approaches can be made. First problem, that is, the reduction of threshold voltage can be solved through ensuring drive current (Ion) while keeping standby current (Ioff) low enough. Also, the other problem, that is, higher operating frequency can be improved by reducing capacitance in devices. From this point of view, a floating body structure in SOI wafer can offer decent benefits for those needs. First of all, digital circuit part will have fast and low leakage system owing to dynamic increase in Ion and decrease in Ioff when implemented on SOI wafer. Second of all, analog circuit part will have much improved speed and wider bandwidth because of smaller capacitance. And finally, the floating body structure introduces dramatic improvement in noise decoupling between digital and analog circuits in mixed-mode application like our structure suggested in this paper. Therefore, our design is very profitable and compatible with SOI technology.

Summary

• Higher Driving Current: Due to the floating body effect, the "off" threshold voltage becomes higher, while the "on" threshold voltage becomes lower. As a result, subthreshold slope improves and leads to a possibility of scaling the power supply down. Additionally it creates the low static power consumption.
• Reduction of Parasitic Capacitance: Because the substrate is floating, the Source & Drain capacitance of the transistor is eleiminated resulting in the improvements of speed. It also contributes the lower dynamic power consumption and higher clock frequency.
• No Body Effect
• Latch-up Immunity: Due to the floating substrate, possibly generated hot carriers do not go through the substrate preventing the substrate voltage from rising up enough to form the forward junction between source and body.
• Improved Density
• Noise Decoupling

Advantages of SOI in this Project

We are now facing a new age of the integrated circuits. According to the roadmap from University of Washington and other institutes, by the year 2010 we have to find out a novel way to break through the scaling problems. At this moment a large number of experiments and possibilities are being pursued for such goals. SOI itself, of course, is one of the greatest promising ways to overcome current limits. Thus, our "Mouse application chip" is not only an excellent current application, but also a very future-compatible-technology-based.

Additional References:

1. Ying-Che Tseng, "AC floating body effects and the resultant analog circuit issues in submicron floating body and body-grounded SOI MOSFET's" in IEEE Electron Device Lett., vol. 46, pp. 1685-1690, August1999.
2. Srinath Krishnan, Jerry G. Fossum, "Grasping SOI Floating-Body Effects," IEEE Circuits and Devices Magazine, July 1998, pp. 32-37.
3. F. Udrea, et al., "SOI Power devices," Electronic & Communication Engineering Journal, February 2000, pp. 27-40.
4. Y. Matsumoto, et al., "Three-axis SOI capacitive accelerometer with PLL C-V converter," Journals of Sensors and Actuators, Vol. A, 1999, pp. 77-85.
5. Ching-Te Chuang, Pong-Fei Lu, and Carl J. Anderson, "SOI for Digital CMOS VLSI: Design considerations and Advances," Proceedings of the IEEE, Vol.86, No. 4, April 1998, pp. 689-720.
6. Ghavam G. Shahidi, et al., "Partially-Depleted SOI Technology for Digital Logic," Proceedings of ISSCC, San Francisco, Feb. 15-18, 1999, pp. 426-427.
7. M. Canada, et al., "A 580MHz RISC Microprocessor in SOI," Proceedings for ISSCC, San Francisco, Feb. 15-18, 1999, pp. 430-431.
8. Young Wug Kim, et al., "A 0.25 mm 600MHz 1.5V SOI ALPHA Microprocessor," proceedings of ISSCC, San Francisco, Feb. 15-18, 1999, pp.432-433.
9. Fari Assaderaghi, "Circuit Styles and Strategies for CMOS VLSI Design on SOI," ISLPED 1999, San Diego, CA, pp.282-287.
10. K. K. Das and R. B. Brown, "Evaluation of Circuit Approaches in Partially-Depleted SOI-CMOS, SOI Conference, Oct. 2-5, 2000, Wakerfield, MA.